The present invention is related to the field of semiconductor processing. More specifically, the present invention is directed to selective deposition of a semiconductor material onto a mixed substrate.
Nowadays, the drive towards heterogeneous integration poses the problem of interconnecting different functional modules (such as e.g. digital complementary metal-oxide-semiconductor (CMOS), analog CMOS, Micro Electro Mechanical Systems (MEMS), and optics) on the same silicon chip. The resulting increase in interconnections requires simplification or adaptation of the existing materials and/or the processing techniques in order to lower the cost, reduce process manufacturing time, and maximize the yield. Additionally, several functional modules (such as, e.g., analog CMOS or MEMS) may require deep trenches or trenches with a high aspect ratio that are typically formed by expensive lithography techniques or plasma etch processing.
The conventional via formation process at interconnect level requires chemical mechanical planarization (CMP) for surface planarization. The latter is known to have numerous limitations such as relatively high costs and defect addition. This in turn reduces the process yield, as determined by the percentage of fully functional dice on a silicon wafer.
In this context, finding alternative processing methods which do not require using CMP has therefore emerged as a valid option.
U.S. Pat. No. 5,431,964 discloses a method of pre-treating a deposition chamber intended to be used for the selective vapor deposition of tungsten, which may allegedly be used in the manufacture of integrated circuits and in particular for the formation of metal interlayer connections.
Despite the progress in the art, there is still a need for an efficient method for the selective deposition of semiconductor material onto a mixed substrate comprising a semiconductor material and an insulator material.
Advantageously, the method of the present invention allows forming narrow trenches or performing trench narrowing, without requiring costly photolithography processing or high aspect ratio etching techniques. In another aspect, the method of the invention may be used for performing gap filling of contacts or vias without requiring CMP techniques.
Other advantages of the invention will be immediately apparent to those skilled in the art from the following description.